AMD floats Venice
AMD has announced that Venice is ramping production. The Epyc server chip does what each past gen has done: added CPU cores and ancillary goodies. However, it's taking a different approach. It's still chiplet-based, but uses silicon bridges (EFB) instead of only a regular (and cheaper) organic packaging substrate to connect them. I/O processing now spans two logic dice, and it appears that serdes (if not also DRAM I/O cells) span two separate dice. The latter change likely reflects implementation challenges and silicon economics. We've seen serdes hewn from the main die in some Ethernet switches, for example. AMD has been the technology leader among merchant-market server-processor suppliers. Intel's getting back on track and remains the sales leader, but that status is increasingly challenged with each Epyc generation.
